1. Field of the Invention
The present invention relates to a voltage controlled oscillator (hereinafter, called VCO) which can control an oscillating frequency by connecting inverting logic circuits of an odd number in a ring and by controlling a delay time in each of the inverting logic circuits with a control voltage.
2. Description of the Related Art
FIG. 6 is a structural view illustrating a conventional VCO of a ring circuit.
The VCO is provided with three delay inverting circuits 1, 2, 3 connected in a ring. These delay inverting circuits 1-3 are logic circuits, each of which compares an input signal received at an input terminal A with a reference voltage Vr applied to an input terminal B and generates a signal of a logic level inverted in accordance with a compared result at an output terminal C. Each of the delay inverting circuits 1-3 is provided with a control terminal D, and controls a delay time of an output signal at an output terminal C with a delay control voltage Vc applied to the control terminal D. That is, each of the delay inverting circuits 1-3 is provided with an inverting circuit comparing the input signal with the reference voltage Vr and generating an inverted signal, and a delay circuit connected to an output of the inverting circuit. The delay circuit comprises a charge part which is a capacitor and a discharge part which is a transistor of which a continuity condition is controlled by the delay control voltage Vc.
The output of the delay inverting circuit 3 is connected to the input of the delay inverting circuit 1 and is provided to a logic gate 4 for wave forming. An oscillating signal OUT of which a waveform is shaped to be rectangular is generated at the output of the logic gate 4.
In this VCO, for example, when the input of the delay inverting circuit 1 is the level "L" at a time that power is supplied, after the delay time by the operation of the delay inverting circuits 1-3, a signal of the level "H" is generated by the output of the delay inverting circuit 3. Since this signal is fed back to the input of the delay inverting circuit 1, after the delay time by the further operation of the delay inverting circuits 1-3, the output of the delay inverting circuit 3 transitions to the "L" level. In this way, the oscillating operation of which a frequency is a ring delay time by the operation of the delay inverting circuits 1-3, is carried out.
Now, the following operation is carried out in each of the delay inverting circuits 1-3. That is, when the output signal from the inverting circuit transitions from the "L" level to the "H" level, the charge part in the delay circuit is charged in a constant short time and the output signal from the delay circuit becomes the "H" level. On the contrary, when the output signal from the inverting circuit transitions from the "H" level to the "L" level, the electric charges held in the charge part are discharged in accordance with a time constant of the discharge part in the delay circuit and the output voltage of the delay circuit lowers continuously. Then, the output signal becomes the "L" level after a time passes. The time constant is controlled by the delay control voltage Vc applied to the delay circuit in the delay inverting circuits 1-3 from the control terminal D, therefore, it is possible to control the oscillating frequency by the delay control voltage Vc.
However, there is a problem in the conventional VCO as follows.
That is, in the control of the oscillating frequency, the delay time, when the output signal in each of the delay inverting circuits 1-3 transitions from the "H" level to the "L" level, is controlled and the ring delay time is controlled, whereby the oscillating frequency is controlled. As to the oscillating signal, the time the signal is at the "H" level is longer than that at the "L" level. Therefore, it is impossible to keep a duty cycle at 50%. As a result, since the pulse width of the "L" level in the oscillating signal OUT becomes narrow, it is impossible to keep a setup time and a hold time for a flip-flop circuit or the like which is connected as a rear stage. Thus, it is caused that a malfunction occurs. Further, though it is possible to set the duty cycle close to 50% by incasing a number of the delay inverting circuits to be a ring, the ring delay time increases. Thus, for example, there is a problem that it becomes difficult to oscillate at a high frequency not less than 156 MHz used for high speed communication.